1. Technical Field
The present disclosure relates to packaging substrates, and, more particularly, to a semiconductor packaging substrate.
2. Description of Related Art
With the development of electronic industry, electronic product designs have trended to be compact-sized and multiple-functioned, and semiconductor package technology has also developed different package types to satisfy various needs in the electronic product designs. In view of the different package types of semiconductor structures, different types of packaging substrate are also developed. A conventional flip-chip packaging substrate has a chip placement region on a surface of the substrate body. A plurality of conductive pads are disposed in the chip placement region, and a solder mask having a plurality of openings for exposing the conductive pads is respectively formed on the substrate body. During a packaging process, a semiconductor chip in the chip placement region is electrically connected to the conductive pads by a flip-chip method.
FIGS. 1A-1E are schematic cross-sectional views at various stages of fabricating a conventional packaging substrate 1.
As shown in FIG. 1A, a substrate body 10 covered by an insulating protective layer 11 is provided, the substrate body 10 has a plurality of conductive pads 100 disposed on a surface thereof, and the insulating protective layer 11 is utilized as a solder mask and has a plurality of openings 110 such that a portion of end surfaces of the conductive pads 100 are exposed by the openings 110, causing the conductive pads 100 to be solder-mask-defined (SMD).
The substrate body 10 includes a dielectric layer 10b and a circuit layer 10a disposed on the dielectric layer 10b (as shown in FIG. 1A′). The circuit layer 10a has a plurality of conductive traces 101 and the conductive pads 100 connected to the conductive traces 101. The end surfaces of the conductive pads 100 are round, and the openings 110 are also round.
As shown in FIG. 1A″, 110 of the insulating protective layer 11 can also expose all end surfaces of the conductive pads 100′ such that the conductive pads 100′ are non-solder-mask-defined.
FIG. 1B shows a subsequent process of FIGS. 1A and 1A′. A resist layer 12 is formed on the insulating protective layer 11, and has a plurality of openings 120 exposing the conductive pads 100 by exposure and development methods. A diameter W of the opening 120 is bigger than a diameter V of the opening 110.
As shown in FIG. 1C, copper bumps 13 are formed by electroplating on the openings 120 such that the conductive pads 100 are electrically connected to the copper bumps 13.
As shown in FIG. 1D, the resist layer 12 is removed.
As shown in FIG. 1E, solder bumps 15 are correspondingly formed on the copper bumps 13 to cover the copper bumps 13.
In the structure of SMD of a conventional packaging substrate 1, since the aligning accuracy e of an exposing machine is, for example, less than or equal to 12.5 μm, as shown in FIG. 1B, the diameter W of an opening 120 of the resist layer 12 is bigger than a diameter V of an opening 110 of the insulating protective layer 11, resulting that the copper bump 13 forms a wing structure 130 (as shown in FIG. 1C). Therefore, a certain spacing P between the solder bumps 15 should be maintained to prevent a bridge connection (as shown in FIG. 1E), and the spacing P between the solder bumps 15 cannot be reduced to, for example, 130 μm or less, in order to satisfy demands for fine-pitch and multi joints.
Moreover, in the conventional SMD, during the performance of Temperature Cycling Test (TCT), because of the great difference between the coefficients of thermal expansion (CTE) of the wing structure 130 and the insulating protective layer 11, the uneven thermal stress may easily cause a crack c at the insulating protective layer 11 under the wing structure 130, as shown in FIG. 1D. The crack c not only reduces the reliability of the packaging substrate 1, but also causes the failure of test for the packaging substrate 1.
Furthermore, because of the formation of the wing structure 130, the diameter v of the opening 110 is less than the greatest diameter of the copper bump 13 (as the diameter w of the wing structure 130) such that the diameter v of the opening 110 may not equal to the greatest diameter of the copper bump 13, as shown in FIG. 1D. Therefore, the reliability of the copper bump 13 cannot be enhanced so that a solder ball may be left off during the push-pull bond test for the solder bump 15.
In addition, in the conventional SMD, as shown in FIG. 1A′, the spacing S between the conductive pad 100 and the conductive traces 101 directly effects the yield. If the spacing S is small, the yield of a circuit is low. However, in the conventional packaging substrate 1, the yield cannot be promoted due to the fact that the spacing S cannot be increased any further.
On the other hand, in the conventional NSMD, as shown in FIG. 1A″, because the contact area between the circuit layer 10a′ and the insulating protective layer 11 is small, compared with the conventional SMD design, the bonding ability between the circuit layer 10a′ and the dielectric layer 10b is worse.
Therefore, there is a need for an improved packaging substrate to address the aforementioned problems in the art.